This application claims priority from Korean Patent Application No. 2005-0015142, filed on Feb. 23, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods thereof, and more particularly, to NAND-type flash memory devices and fabrication methods thereof.
2. Description of the Related Art
In general, information stored in a non-volatile memory device, such as a flash memory device, is retained even if its power supply is cut off. Because of this advantage, the flash memory device is popular and widely used in a memory card, as well as other applications. Generally, the flash memory device can be classified into NAND-type flash memory devices and NOR-type flash memory devices. Among the architecture of these flash memory devices, a cell array region of a NAND-type flash memory device includes a plurality of transistor circuit strings. Each of these strings generally includes a string selection transistor, cell transistors, and a ground selection transistor, which are connected to each other in series. A drain region of the string selection transistor may be electrically connected to a bit line through a bit line contact plug, and a source region of the ground selection transistor may be electrically connected to a common source line (CSL).
A method of fabricating a NAND-type flash memory device is disclosed in U.S. Pat. No. 6,790,729 entitled “Method of manufacturing NAND flash memory device”, by Woo. According to U.S. Pat. No. 6,790,729, an interlayer insulating layer on a semiconductor substrate is patterned to form a common source line contact hole, and a conductive layer fills the common source line contact hole to form a common source line (CSL). An insulating layer is formed on the entire surface of the semiconductor substrate having the common source line. Subsequently, the insulating layer is subjected to a damascene process to form a plurality of damascene patterns. The damascene patterns expose a predetermined region and a cell drain region of the common source line as well as a gate and a source/drain region of a peripheral transistor. Subsequently, a process of filling a metal layer in the damascene patterns is performed to form a metal interconnection connected to the common source line, a bit line connected to the cell drain region, and metal interconnections connected to the gate and the source/drain region of the peripheral transistor. According to this patent, the number of fabricating processes can be reduced compared with the conventional method of fabricating the NAND-type flash memory device. However, the NAND-type memory device according to U.S. Pat. No. 6,790,729 has a structure that may make it difficult to simplify its fabricating process.
Processes of forming fine and intricate patterns associated with highly integrated semiconductor devices have recently been developed, and thus fabricating costs have increased. This fabricating cost increase is a main reason for a productivity decrease of semiconductor devices. Accordingly, it is necessary to provide a structure of a semiconductor device and a method of its fabrication that can increase the productivity of the semiconductor device while reducing its fabrication costs.